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one-pll general-purpose flash-programmable and 2-wire serially programmable clock generato r cy22150 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07104 rev. *g revised december 5, 2004 features ? integrated phase-locked loop (pll) ? commercial and industrial operation ? flash-programmable ? field-programmable ? 2-wire serial programming interface ? low-skew, low-jitter, high-accuracy outputs ? 3.3v operation with 2.5v output option ? 16-lead tssop benefits ? internal pll to generate six outputs up to 200 mhz. able to generate custom frequencies from an external crystal or a driven source. ? performance guaranteed for applications that require an extended temperature range. ? nonvolatile reprogrammable technology allows easy customization, quick turnaround on design changes and product performance enhancements, and better inventory control. parts can be reprogrammed up to 100 times, reducing inventory of custom parts and providing an easy method for upgrading existing designs. ? the cy22150 can be programmed at the package level. in-house programming of samples and prototype quantities is available using the cy3672 ftg devel- opment kit. production quantities are available through cypress?s value-added distribution partners or by using third party programmers from bp micro- systems ? , hilo systems ? , and others. ? the cy22150 provides an industry-standard interface for volatile, system-level customization of unique frequencies and options. serial programming and reprogramming allows quick design changes and product enhancements, eliminates inventory of old design parts, and simplifies manufacturing. ? high performance suited for commercial, industrial, networking, telecomm and other general-purpose applications. ? application compatibility in standard and low-power systems. ? industry-standard packaging saves on board space . logic block diagram spi control vddl avdd vss avss sdat sclk serial vssl vdd xin xout lclk1 divider pll osc. lclk3 q p vco lclk2 lckl4 clk5 clk6 bank 1 divider bank 2 crosspoint switch 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vss vssl sclk lclk1 xin xout vdd sdat avss lclk3 lclk2 clk6 clk5 avdd vddl lclk4 pin configuration programming interface matrix
cy22150 document #: 38-07104 rev. *g page 2 of 13 frequency calculation and register definitions the cy22150 is an extremely flexible clock generator with four basic variables that can be used to determine the final output frequency. they are the input reference frequency (ref), the internally calculated p and q dividers, and the post divider, which can be a fixed or calculated value. there are three basic formulas for determining the final output frequency of a cy22150-based design: ? clk = ((ref * p)/q)/post divider ? clk = ref/post divider ?clk = ref. the basic pll block diagram is shown in figure 1 . each of the six clock outputs on the cy22150 has a total of seven output options available to it. there are six post divider options available: /2 (two of these), /3, /4, /div1n and /div2n. div1n and div2n are independently calculated and are applied to individual output groups. the post divider options can be applied to the calculated vco frequency ((ref*p)/q) or to the ref directly. in addition to the six post divider output options, the seventh option bypasses the pll and pa sses the ref directly to the crosspoint switch matrix. note: 1. float xout if xin is driven by an external clock source. part number outputs input frequency range output frequency range specifications cy22150fc 6 8 mhz?30 mhz (external crystal) 1 mhz?133 mhz (driven clock) 80 khz?200 mhz (3.3v) 80 khz?166.6 mhz (2.5v) field programmable serially programmable commercial temperature cy22150fi 6 8 mhz?30 mhz (external crystal) 1 mhz?133 mhz (driven clock) 80 khz ? 166.6 mhz (3.3v) 80 khz ? 150 mhz (2.5v) field programmable serially programmable industrial temperature pin definitions pin name pin number pin description xin 1 reference input . driven by a crystal (8 mhz ? 30 mhz) or external clock (1 mhz ? 133 mhz). programmable input load capacitors allow for maximum flexibility in selecting a crystal, regardless of manufacturer, pr ocess, performance, or quality. vdd 2 3.3v voltage supply avdd 3 3.3v analog voltage supply sdat 4 serial data input avss 5 analog ground vssl 6 lclk ground lclk1 7 configurable clock output 1 at v ddl level (3.3v or 2.5v) lclk2 8 configurable clock output 2 at v ddl level (3.3v or 2.5v) lclk3 9 configurable clock output 3 at v ddl level (3.3v or 2.5v) sclk 10 serial clock input vddl 11 lclk voltage supply (2.5v or 3.3v) lclk4 12 configurable clock output 4 at v ddl level (3.3v or 2.5v) vss 13 ground clk5 14 configurable clock output 5 (3.3v) clk6 15 configurable clock output 6 (3.3v) xout [1] 16 reference output
cy22150 document #: 38-07104 rev. *g page 3 of 13 default start-up condition for the cy22150 the default (programmed) condit ion of the device is generally set by the distributor who programs the device using a customer-specific jedec f ile produced by cyclocksrt ? . parts shipped from the factory are blank and unprogrammed. in this condition, all bits are set to 0, all outputs are three-stated, and the crystal oscillator circuit is active. while you can develop your own subroutine to program any or all of the individual registers described in the following pages, it may be easier to use cyclocksrt to produce the required register setting file. the serial interface address of the cy22150 is 69h. should there be a conflict with any other devices in your system, this can also be changed using cyclocksrt. frequency calculations and register defini- tions using the serial programming interface the cy22150 provides an industry standard serial interface for volatile, in-system programming of unique frequencies and options. serial programming and reprogramming allows for quick design changes and product enhancements, eliminates inventory of old design parts, and simplifies manufacturing. the serial programming interface (spi) provides volatile programming, i.e., when the target system is powered down, the cy22150 reverts to its pre-spi state, as defined above (programmed or unprogra mmed). when the system is powered back up again, the spi registers will need to be reconfigured again. all programmable registers in the cy22150 are addressed with eight bits and contain eight bits of data. the cy22150 is a slave device with an address of 1101001 (69h). table 1 lists the spi registers and their definitions. specific register definitions and their allowable values are listed below. reference frequency the ref can be a crystal or a driven frequency. for crystals, the frequency range must be between 8 mhz and 30 mhz. for a driven frequency, the frequency range must be between 1 mhz and 133 mhz. using a crystal as the reference input the input crystal oscillator of the cy22150 is an important feature because of the flexibility it allows the user in selecting a crystal as a ref source. the input oscillator has program- mable gain, allowing for maximum compatibility with a reference crystal, regardless of manufacturer, process, perfor- mance and quality. programmable crystal input oscillator gain settings the input crystal oscillator gain (xdrv) is controlled by two bits in register 12h, and are set according to table 2 . the parameters controlling the gain are the crystal frequency, the internal crystal parasitic resist ance (esr, available from the (q+2) vco (2(pb+4)+po) /2 /3 /2 lclk1 lclk2 lclk3 lclk4 clk5 clk6 clksrc crosspoint switch matrix [44h] [44h] [44h,45h] [45h] [45h,46h] div2clk ref pfd divider bank 1 [45h] div1src [och] /4 div2src [47h] divider bank 2 div1n [och] div2n [47h] div1clk /div1n 1 0 1 0 [42h] [40h], [41h], [42h] /div2n qtotal ptotal clkoe [09h] figure 1. basic block diagram of cy22150 pll
cy22150 document #: 38-07104 rev. *g page 4 of 13 manufacturer), and the capload setting during crystal start-up. bits 3 and 4 of register 12h c ontrol the input crystal oscillator gain setting. bit 4 is the msb of the setting, and bit 3 is the lsb. the setting is programmed according to ta ble 2 . all other bits in the register are reserved and should be programmed as shown in table 3 . using an external clock as the reference input the cy22150 can also accept an external clock as reference, with speeds up to 133 mhz. with an external clock, the xdrv (register 12h) bits must be set according to table 4 . table 1. summary table ? cy22150 programmable registers register description d7 d6 d5 d4 d3 d2 d1 d0 09h clkoe control 0 0 clk6 clk5 lclk4 lclk3 lclk2 lclk1 och div1src mux and div1n divider div1src div1n(6) div1n(5) div1n(4) d iv1n(3) div1n(2) div1n(1) div1n(0) 12h input crystal oscillator drive control 001xdrv(1)xdrv(0)000 13h input load capacitor control capload (7) capload (6) capload (5) capload (4) capload (3) capload (2) capload (1) capload (0) 40h charge pump and pb counter 1 1 0 pump(2) pump(1) pump(0) pb(9) pb(8) 41h pb(7) pb(6) pb(5) pb(4) pb(3) pb(2) pb(1) pb(0) 42h po counter, q counter po q(6) q(5) q(4) q(3) q(2) q(1) q(0) 44h crosspoint switch matrix control clksrc2 for lclk1 clksrc1 for lclk1 clksrc0 for lclk1 clksrc2 for lclk2 clksrc1 for lclk2 clksrc0 for lclk2 clksrc2 for lclk3 clksrc1 for lclk3 45h clksrc0 for lclk3 clksrc2 for lclk4 clksrc1 for lclk4 clksrc0 for lclk4 clksrc2 for clk5 clksrc1 for clk5 clksrc0 for clk5 clksrc2 for clk6 46h clksrc1 for clk6 clksrc0 for clk6 111111 47h div2src mux and div2n divider div2src div2n(6) div2n(5) div2n(4) d iv2n(3) div2n(2) div2n(1) div2n(0) table 2. programmable crystal input oscillator gain settings cap register settings 00h ? 80h 80h ? c0h c0h ? ffh effective load capacitance (capload) 6 pf to 12 pf 12pf to 18pf 18pf to 30pf crystal esr 30 ? 60 ? 30 ? 60 ? 30 ? 60 ? crystal input frequency 8 ? 15 mhz 000101100110 15 ? 20 mhz 011001101010 20 ? 25 mhz 011010101011 25 ? 30 mhz 10 10 10 11 11 n/a table 3. bit locations and values address d7 d6 d5 d4 d3 d2 d1 d0 12h 0 0 1 xdrv(1) xdrv(0) 0 0 0 table 4. programmable external reference input oscillator drive settings reference frequency 1 ? 25 mhz 25 ? 50 mhz 50 ? 90 mhz 90 ? 133 mhz drive setting 00 01 10 11
cy22150 document #: 38-07104 rev. *g page 5 of 13 input load capacitors input load capacitors allow the user to set the load capacitance of the cy22150 to match the input load capacitance from a crystal. the value of the input load capacitors is determined by 8 bits in a programmable register [13h]. total load capacitance is determined by the formula: capload = (c l ? c brd ? c chip )/0.09375 pf where: ?c l = specified load capacitance of your crystal. ?c brd = the total board capacitance, due to external capac- itors and board trace capacitanc e. in cyclocksrt, this value defaults to 2 pf. ?c chip = 6 pf. ? 0.09375 pf = the step resolution available due to the 8-bit register. in cyclocksrt, only the crystal capacitance (c l ) is specified. c chip is set to 6 pf, and c brd defaults to 2 pf. if your board capacitance is higher or lower than 2 pf, the formula above can be used to calculate a new capload value and programmed into register 13h. in cyclocksrt, enter the crystal capacitance (c l ). the value of capload will be determined automatically and programmed into the cy22150. through the sdat and sclk pins, the value can be adjusted up or down if your board capacitance is greater or less than 2 pf. for an external clock source, capload defaults to 0. see table 5 for capload bit locations and values. the input load capacitors are placed on the cy22150 die to reduce external component cost. these capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when non-linear load capacitance is affected by load, bias, supply and temperature changes. pll frequency, q counter [42h(6..0)] the first counter is known as the q counter. the q counter divides ref by its calculated value. q is a 7 bit divider with a maximum value of 127 and minimum value of 0. the primary value of q is determined by 7 bits in register 42h (6..0), but 2 is added to this register value to achieve the total q, or q total . q total is defined by the formula: q total = q + 2 the minimum value of q total is 2. the maximum value of q total is 129. register 42h is defined in the table. stable operation of the cy22150 cannot be guaranteed if ref/q total falls below 250 khz. q total bit locations and values are defined in ta ble 6 . pll frequency, p counter [40h(1..0)], [41h(7..0)], [42h(7) the next counter definition is the p (product) counter. the p counter is multiplied with the (ref/q total ) value to achieve the vco frequency. the product counter, defined as p total , is made up of two internal variables, pb and po. the formula for calculating p total is: p total = (2(pb + 4) + po) . pb is a 10-bit variable, defined by registers 40h(1:0) and 41h(7:0). the 2 lsbs of regi ster 40h are the two msbs of variable pb. bits 4..2 of register 40h are used to determine the charge pump settings (see section 5). the 3 msbs of register 40h are preset and reserved and cannot be changed. po is a single bit variable, defined in register 42h(7). this allows for odd numbers in p total . the remaining seven bits of 42h are used to define the q counter, as shown in ta ble 6 . the minimum value of p total is 8. the maximum value of p total is 2055. to achieve the minimum value of p total , pb and po should both be programmed to 0. to achieve the maximum value of p total , pb should be programmed to 1023, and po should be programmed to 1. stable operation of the cy22150 cannot be guaranteed if the value of (p total *(ref/q total )) is above 400 mhz or below 100 mhz. registers 40h, 41h and 42h are defined in table 7 . pll post divider options [och(7..0)], [47h(7..0)] the output of the vco is routed through two independent muxes, then to two divider banks to determine the final clock output frequency. the mux determines if the clock signal feeding into the divider banks is the calculated vco frequency or ref. there are two select muxes (div1src and div2src) and two divider banks (divider bank 1 and divider bank 2) used to determine this clock signal. the clock signal passing through div1src and div2src is referred to as div1clk and div2clk, respectively. the divider banks have 4 unique divider options available: /2, /3, /4, and /divxn. divxn is a variable that can be indepen- dently programmed (div1n and div2n) for each of the two divider banks. the minimum value of divxn is 4. the maximum value of divxn is 127. a value of divxn below 4 is not guaranteed to work properly. div1src is a single bit variable, controlled by register och. the remaining seven bits of register och determine the value of post divider div1n. div2src is a single bit variable, controlled by register 47h. the remaining seven bits of register 47h determine the value of post divider div2n. register och and 47h are defined in table 8 . charge pump settings [40h(2..0)] the correct pump setting is important for pll stability. charge pump settings are controlled by bi ts (4..2) of register 40h, and are dependent on internal variable pb (see ? pll frequency, p counter[40h(1..0)], [41h(7..0)], [42h(7)] ?). table 9 summa- rizes the proper charge pump settings, based on ptotal. see ta ble 10 for register 40h bit locations and values. table 5. input load capacitor register bit settings address d7 d6 d5 d4 d3 d2 d1 d0 13h capload(7) capload(6) capload(5) capload(4) capload(3) capload(2) capload(1) capload(0)
cy22150 document #: 38-07104 rev. *g page 6 of 13 although using the above table will guarantee stability, it is recommended to use the print preview function in cyclocksrt to determine the correct charge pump settings for optimal jitter performance. pll stability cannot be guaranteed for values below 16 and above 1023. if values above 1023 are needed, use cyclocksrt to determine th e best charge pump setting. clock output settings: cl ksrc ? clock output cross- point switch matrix [44h(7.. 0)], [45h(7..0)], [46h(7..6)] clkoe ? clock output enab le control [09h(5..0)] every clock output can be defined to come from one of seven unique frequency sources. the clksrc(2..0) crosspoint switch matrix defines which source is attached to each individual clock output. clksrc(2..0) is set in registers 44h, 45h, and 46h. the remainder of register 46h(5:0) must be written with the values stated in the register table when writing register values 46h(7:6). in addition, each clock output has individual clkoe control, set by register 09h(5..0). when div1n is divisible by four, then clksrc(0,1,0) is guaranteed to be rising edge phase-aligned with clksrc(0,0,1). when div1n is six, then clksrc(0,1,1) is guaranteed to be rising edge phase-aligned with clksrc(0,0,1). when div2n is divisible by four, then clksrc(1,0,1) is guaranteed to be rising edge phase-aligned with clksrc(1,0,0). when div2n is divisible by eight, then clksrc(1,1,0) is guaranteed to be rising edge phase-aligned with clksrc(1,0,0). each clock output has its own output enable, controlled by register 09h(5..0). to enable an output, set the corresponding clkoe bit to 1. clko e settings are in table 13 . the output swing of lclk1 through lclk4 is set by v ddl . the output swing of clk5 and clk6 is set by v dd . test, reserved, and blank registers writing to any of the following registers will cause the part to exhibit abnormal behavior, as follows. [00h to 08h] ? reserved [0ah to 0bh] ? reserved [0dh to 11h] ? reserved [14h to 3fh] ? reserved [43h] ? reserved [48h to ffh] ? reserved. table 6. p counter register definition addressd7d6d5d4d3d2d1d0 40h 1 1 0 pump(2) pump(1) pump(0) pb(9) pb(8) 41h pb(7) pb(6) pb(5) pb(4) pb(3) pb(2) pb(1) pb(0) 42h po q(6) q(5) q(4) q(3) q(2) q(1) q(0) table 7. p counter register definition addressd7d6d5d4d3d2d1d0 40h 1 1 0 pump(2) pump(1) pump(0) pb(9) pb(8) 41h pb(7) pb(6) pb(5) pb(4) pb(3) pb(2) pb(1) pb(0) 42h po q(6) q(5) q(4) q(3) q(2) q(1) q(0) table 8. pll post divider options address d7 d6 d5 d4 d3 d2 d1 d0 och div1src div1n(6) div1 n(5) div1n(4) div1n(3) di v1n(2) div1n(1) div1n(0) 47h div2src div2n(6) div2 n(5) div2n(4) div2n(3) di v2n(2) div2n(1) div2n(0) table 9. charge pump settings charge pump setting ? pump(2..0) calculated p total 000 16 ? 44 001 45 ? 479 010 480 ? 639 011 640 ? 799 100 800 ? 1023 101, 110, 111 do not us e ? device will be unstable table 10.register 40h ch ange pump bit settings address d7 d6 d5 d4 d3 d2 d1 d0 40h 1 1 0 pump(2) pump(1) pump(0) pb(9) pb(8)
cy22150 document #: 38-07104 rev. *g page 7 of 13 programmable interface timing the cy22150 utilizes a 2-wire serial-interface sdat and sclk that operates up to 400 kbits/second in read or write mode. the basic write serial format is as follows. start bit; seven-bit device address (da); r/w bit; slave clock acknowledge (ack); eight-bit memory address (ma); ack; eight-bit data; ack; eight-bit dat a in ma + 1 if desired; ack; eight-bit data in ma+2; ack; etc. until stop bit.the basic serial format is illustrated in figure 3 . data valid data is valid when the clock is high, and may only be transi- tioned when the clock is low, as illustrated in figure 2 . data frame every new data frame is indicated by a start and stop sequence, as illustrated in figure 4 . start sequence ? start frame is indicated by sdat going low when sclk is high. every time a start signal is given, the next eight-bit data must be the device address (seven bits) and a r/w bit, followed by register address (eight bits) and register data (eight bits). stop sequence ? stop frame is indicated by sdat going high when sclk is high. a stop frame frees the bus for writing to another part on the same bus or writing to another random register address. acknowledge pulse during write mode, the cy22150 will respond with an ack pulse after every eight bits. this is accomplished by pulling the sdat line low during the n*9 th clock cycle, as illustrated in figure 5 . (n = the number of eight -bit segments transmitted.) during read mode, the ack pulse after the data packet is sent is generated by the master. table 11. clksrc2 clksrc1 clksrc0 definition and notes 0 0 0 reference input. 0 0 1 div1clk/div1n. div1n is defined by register [och]. allowable values for div1n are 4 to 127. if divider bank 1 is not being used, set div1n to 8. 0 1 0 div1clk/2. fixed /2 divider opt ion. if this option is used, div1n must be divisible by 4. 0 1 1 div1clk/3. fixed /3 divider option. if this option is used, set div1n to 6. 1 0 0 div2clk/div2n. div2n is defined by register [47h ]. allowable values for div2n are 4 to 127. if divider bank 2 is not being used, set div2n to 8. 1 0 1 div2clk/2. fixed /2 divider opt ion. if this option is used, div2n must be divisible by 4. 1 1 0 div2clk/4. fixed /4 divider opt ion. if this option is used, div2n must be divisible by 8. 1 1 1 reserved ? do not use. table 12. addressd7d6d5d4d3d2d1d0 44h clksrc2 for lclk1 clksrc1 for lclk1 clksrc0 for lclk1 clksrc2 for lclk2 clksrc1 for lclk2 clksrc0 for lclk2 clksrc2 for lclk3 clksrc1 for lclk3 45h clksrc0 for lclk3 clksrc2 for lclk4 clksrc1 for lclk4 clksrc0 for lclk4 clksrc2 for clk5 clksrc1 for clk5 clksrc0 for clk5 clksrc2 for clk6 46h clksrc1 for clk6 clksrc0 for clk6 111111 table 13.clkoe bit setting address d7 d6 d5 d4 d3 d2 d1 d0 09h 0 0 clk6 clk5 lclk4 lclk3 lclk2 lclk1 figure 2. data valid and data transition periods sdat sclk data valid transition to next bit clk low clk high v ih v il t su t dh
cy22150 document #: 38-07104 rev. *g page 8 of 13 figure 3. data frame architecture figure 4. start and stop frame figure 5. frame format (device address, r/w , register address, register data sdat write start signal device address 7-bit r/w = 0 1-bit 8-bit register address slave 1-bit ack slave 1-bit ack 8-bit register data stop signal multiple contiguous registers slave 1-bit ack 8-bit register data (xxh) (xxh) (xxh+1) slave 1-bit ack 8-bit register data (xxh+2) slave 1-bit ack 8-bit register data (ffh) slave 1-bit ack 8-bit register data (00h) slave 1-bit ack slave 1-bit ack sdat read start signal device address 7-bit r/w = 0 1-bit 8-bit register address slave 1-bit ack slave 1-bit ack 7-bit device stop signal multiple contiguous registers 1-bit r/w = 1 8-bit register data (xxh) address (xxh) master 1-bit ack 8-bit register data (xxh+1) master 1-bit ack 8-bit register data (ffh) master 1-bit ack 8-bit register data (00h) master 1-bit ack master 1-bit ack sdat sclk start transition to next bit stop sdat sclk da6 da5da0 r/w ack ra7 ra6 ra1 ra0 ack stop start ack d7 d6 d1 d0 +++ + + + parameter description min. max. unit f sclk frequency of sclk 400 khz start mode time from sda low to scl low 0.6 s clk low sclk low period 1.3 s clk high sclk high period 0.6 s t su data transition to sclk high 100 ns t dh data hold (sclk low to data transition) 0 ns rise time of sclk and sdat 300 ns fall time of sclk and sdat 300 ns stop mode time from sclk high to sdat high 0.6 s stop mode to start mode 1.3 s
cy22150 document #: 38-07104 rev. *g page 9 of 13 applications controlling jitter jitter is defined in many ways including: phase noise, long-term jitter, cycle to cycle jitter, period jitter, absolute jitter, and deterministic. these jitter terms are usually given in terms of rms, peak to peak, or in the case of phase noise dbc/hz with respect to the fundamental frequency. power supply noise and clock output loading are two major system sources of clock jitter. power supply noise can be mitigated by proper power supply decoupling (0.1 f ceramic cap 0.25?) of the clock and ensuring a low impedance ground to the chip. reducing capacitive clock output loading to a minimum lowers current spikes on the clock edges and thus reduces jitter. reducing the total number of active outputs will also reduce jitter in a linear fashion. however, it is better to use two outputs to drive two loads than one output to drive two loads. the rate and magnitude that the pll corrects the vco frequency is directly related to jitter performance. if the rate is too slow, then long term jitter and phase noise will be poor. therefore, to improve long-term jitter and phase noise, reducing q to a minimum is advisable. this technique will increase the speed of the phase frequency detector which in turn drive the input voltage of the vco. in a similar manner increasing p till the vco is near its maximum rated speed will also decrease long term jitter and phase noise. for example: input reference of 12 mhz; desired output frequency of 33.3 mhz. one might arrive at the following solution: set q = 3, p = 25, post div = 3. however, the best jitter results will be q = 2, p = 50, post div = 9. for more information, refer to the application note ? jitter in pll-based systems: causes , effects, and solutions ? available at http://www.cypress.com/clock/appnotes.html, or contact your local cypress field applications engineer. test circuit 0.1 mf v dd 0.1 mf av dd clk out c load gnd outputs v ddl 0.1 f t3 clk 80% 20% t4 figure 6. duty cycle definition; dc = t2/t1 t1 t2 clk 50% 50% figure 7. rise and fall time definitions t6 figure 8. peak-to-peak jitter
cy22150 document #: 38-07104 rev. *g page 10 of 13 absolute maximum conditions parameter description min. max. unit v dd supply voltage ?0.5 7.0 v v ddl i/o supply voltage ?0.5 7.0 v t s storage temperature [2] ?65 125 c t j junction temperature 125 c package power dissipation ? commercial temp 450 mw package power dissipation ? industrial temp 380 mw digital inputs av ss ? 0.3 av dd + 0.3 v digital outputs referred to v dd v ss ? 0.3 v dd + 0.3 v digital outputs referred to v ddl v ss ? 0.3 v ddl +0.3 v esd static discharge voltage per mil-std-833, method 3015 2000 v recommended operating conditions parameter description min. typ. max. unit v dd operating voltage 3.135 3.3 3.465 v vddl hi [3] operating voltage 3.135 3.3 3.465 v vddl lo [3] operating voltage 2.375 2.5 2.625 v t ac ambient commercial temp 0 70 c t ai ambient industrial temp ?40 85 c c load max. load capacitance, v dd /v ddl = 3.3v 15 pf c load max. load capacitance, v ddl = 2.5v 15 pf f refd driven ref 1 133 mhz f refc crystal ref 8 30 mhz t pu power-up time for all vdds to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms dc electrical characteristics parameter [4] name description min. typ. max. unit i oh3.3 output high current v oh = v dd ? 0.5, v dd /v ddl = 3.3v (sink) 12 24 ma i ol3.3 output low current v ol = 0.5, v dd /v ddl = 3.3v (source) 12 24 ma i oh2.5 output high current v oh = v ddl ? 0.5, v ddl = 2.5v (source) 8 16 ma i ol2.5 output low current v ol = 0.5, v ddl = 2.5v (sink) 8 16 ma v ih input high voltage cmos levels, 70% of v dd 0.7 v dd v il input low voltage cmos levels, 30% of v dd 0.3 v dd c in input capacitance sclk and sdat pins 7 pf i iz input leakage current sclk and sdat pins 5 a v hys hysteresis of schmitt triggered inputs sclk and sdat pins 0.05 v dd i vdd [5,6] supply current av dd /v dd current 45 ma i vddl3.3 [5,6] supply current v ddl current (v ddl = 3.465v) 25 ma i vddl2.5 [5,6] supply current v ddl current (v ddl = 2.625v) 17 ma notes: 2. rated for 10 years. 3. v ddl is only specified and characterized at 3.3v 5% and 2.5v 5%. v ddl may be powered at any value between 3.465v and 2.375v. 4. not 100% tested. 5. i vdd currents specified for two clk outputs running at 125 mhz, two lclk outputs running at 80 mhz, and two lclk outputs running at 66.6 mhz. 6. use cyclocksrt to calculate actual i vdd and i vddl for specific output fr equency configurations.
cy22150 document #: 38-07104 rev. *g page 11 of 13 ac electrical characteristics parameter [7] name description min. typ. max. unit t1 output frequency, commercial temp clock output limit, 3.3v 0.08 (80 khz) 200 mhz clock output limit, 2.5v 0.08 (80 khz) 166.6 mhz output frequency, industrial temp clock output limit, 3.3v 0.08 (80 khz) 166.6 mhz clock output limit, 2.5v 0.08 (80 khz) 150 mhz t2 lo output duty cycle duty cycle is defined in figure 6 ; t1/t2 fout < 166 mhz, 50% of v dd 45 50 55 % t2 hi output duty cycle duty cycle is defined in figure 6 ; t1/t2 fout > 166 mhz, 50% of v dd 40 50 60 % t3 lo rising edge slew rate (v ddl = 2.5v) output clock rise time, 20% ? 80% of v ddl . defined in figure 7 . 0.6 1.2 v/ns t4 lo falling edge slew rate (v ddl = 2.5v) output dlock fall time, 80% ? 20% of v ddl . defined in figure 7 . 0.6 1.2 v/ns t3 hi rising edge slew rate (v ddl = 3.3v) output dlock rise time, 20% ? 80% of v dd /v ddl . defined in figure 7 . 0.8 1.4 v/ns t4 hi falling edge slew rate (v ddl = 3.3v) output dlock fall time, 80% ? 20% of v dd /v ddl . defined in figure 7 . 0.8 1.4 v/ns t5 [8] skew output-output skew between related outputs. 250 ps t6 [9] clock jitter peak-to-peak period jitter 250 ps t10 pll lock time 0.30 3 ms device characteristics parameter name value unit ja theta ja 115 c/w complexity transistor count 74,600 transistors ordering information ordering code package type operating range operating voltage cy22150fc 16-lead tssop commercial (0 to 70c) 3.3v cy22150fct 16-lead tssop - tape and reel commercial (0 to 70c) 3.3v cy22150fi 16-lead tssop industrial (?40 to 85c) 3.3v cy22150zc-xxx [10] 16-lead tssop commercial (0 to 70c) 3.3v cy22150zc-xxxt [10] 16-lead tssop - tape and reel commercial (0 to 70c) 3.3v CY22150ZI-XXX [10] 16-lead tssop industrial (?40 to 85c) 3.3v CY22150ZI-XXXt [10] 16-lead tssop- tape and reel industrial (?40 to 85c) 3.3v cy3672 ftg development system cy3672adp000 cy22150f socket lead free cy22150fzxc 16-lead tssop commercial (0 to 70c) 3.3v cy22150fzxct 16-lead tssop - tape and reel commercial (0 to 70c) 3.3v cy22150fzxi 16-lead tssop industrial (?40 to 85c) 3.3v cy22150fzxit 16-lead tssop - tape and reel industrial (?40 to 85c) 3.3v cy22150zxc-xxx [10] 16-lead tssop commercial (0 to 70c) 3.3v cy22150zxc-xxxt [10] 16-lead tssop- tape and reel commercial (0 to 70c) 3.3v cy22150zxi-xxx [10] 16-lead tssop industrial (?40 to 85c) 3.3v cy22150zxi-xxxt [10] 16-lead tssop- tape and reel industrial (?40 to 85c) 3.3v notes: 7. not 100% tested, guaranteed by design. 8. skew value guaranteed when outputs are generated from the same divider bank. see logic diagram for more information. 9. jitter measurement will vary. actual jitter is dependent on xin ji tter and edge rate, number of active outputs, output freque ncies, v ddl , (2.5v or 3.3v jitter in ? pll-based systems: causes, effects, and solutions ,? available at http://wwww.cypress.com/clock/appnotes. html, or contact your lo cal cypress field applica- tions engineer). 10. the cy22150zc-xxx and CY22150ZI-XXX are factory programmed config urations. factory programming is available for high-volume design opportunities of 100ku/year or more in production. for more details, contac t your local cypress fae or cypress sales representative.
cy22150 document #: 38-07104 rev. *g page 12 of 13 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagram bp microsystems is a trademark of bp microsystems. hilo systems is a trademark of hi-lo systems, inc. cyclocks is a trademark of cypress semiconductor. all product and company names mentio ned in this document are the trademarks of their respective holders. 4.90[0.193] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 16 pin1id 6.50[0.256] seating plane 1 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] bsc. 5.10[0.200] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] bsc 0.25[0.010] 0-8 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] plane gauge dimensions in mm[inches] min. max. reference jedec mo-153 package weight 0.05 gms part # z16.173 standard pkg. zz16.173 lead free pkg. 16-lead tssop 4.40 mm body z16.173 51-85091-*a
cy22150 document #: 38-07104 rev. *g page 13 of 13 document history page document title: cy22150 one-pll general-purpose flash- programmable and 2-wire serially-programmable clock generator document number: 38-07104 rev. ecn no. issue date orig. of change description of change ** 107498 08/08/01 ckn new data sheet *a 110043 02/06/02 ckn preliminary to final *b 113514 05/01/02 ckn removed overline on figure 5 register address register data changed clk high unit from ns to s in parameter description table added (sink) to rows 1 and 4 and added (source) to rows 2 and 3 in the dc electrical characteristics table ( figure ) *c 121868 12/14/02 rbi power-up requirements added to operating conditions information *d 125453 05/19/03 ckn changed 0 to 1 under 12h/d5 of table 1 and table 3 . reworded and reformatted programmable crystal input oscillator gain settings text. *e 242808 see ecn rgl minor change: fixed the broken line in the block diagram *f 252352 see ecn rgl corrected table 2 specs. *g 296084 see ecn rgl added lead free devices

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